![]() With Verilog, you generally won’t create flip flops directly, but will let the compiler infer them from your code. There are other kinds of flip flops, like the T flip flop (which toggles state) or the JK flip flop which can perform several functions. A D flip flop will remember its input (named D) at the clock edge and hold that output until the next clock edge. If you need a refresher on flip flops, they are elements that remember a single bit. This makes things much simpler to design. Now the circuit will work fine if the longest delay from one flip flop’s output to the next flip flop’s input is less than the period of the clock. The most common solution to this is to only “look” at the signals (and store them in a flip flop) on a clock edge (usually, just the rising edge). But the errors will add up and in a more complex circuit it would be easy to get glitches while the inputs to combinatorial gates change with different delays. So there’s some small period of time where the output is “wrong.” For a single gate, this probably isn’t a big deal since the delay is probably minuscule. On paper, that seems reasonable, but in real life, the two signals might not arrive at the same time. ![]() Then imagine both inputs go from zero to one, which should take the output from zero to one, also. Why Clocks?Ĭlocks are an important part of practical digital design. This time, we’ll finish the demo design and add two clocked elements: a latch that remembers if the adder has ever generated a carry and also some counters to divide the 12 MHz clock down to a half-second pulse to blink some of the onboard LEDs. The adder is a combinatorial circuit and didn’t use a clock. ![]() Last time I talked about how to create an adder in Verilog with an eye to putting it into a Lattice iCEstick board. ![]()
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